The Trench-type Vertical MOSFET, or simply Trench MOS, is widely used in power control electronics due to their efficient structure and low specific ON resistance.
FIGS. 7(a) to 7(f) are cross-sectional diagrams illustrating the steps of producing the prior art typical structure of an N-channel Trench MOSFET (see Non-Patent Reference 1, for example). Two key parameters in the Trench MOSFET are (a) the breakdown voltage (hereinafter, the voltage will be referred to as “BVdss” sometimes), and (b) the ON resistance (hereinafter, the resistance will be referred to as “RON” sometimes).
The physical location of respective components of the MOSFET, and meaning of the different components of the ON resistance are illustrated in FIG. 8. In this figure, Rs is the resistance of the diffusion and contact resistance component of the source region, Rch is the resistance of the induced MOSFET channel, Racc is the resistance of the accumulation region of the gate and the drain, Rdrift is the resistance of the low-doped drain region, and Rsub is the resistance of the highly doped drain (substrate) region.
The relationship described by the following formula is satisfied between the ON resistance (Ron) of the MOSFET and the components of the resistances shown in FIG. 8:RON=Rsub+Rch+Racc+Rdrift+Rsub.In general, there is a tradeoff between RON and BVdss since to get a high breakdown voltage (BVdss), a low impurity doped drift region is needed. This results in an increase in Rdrift and therefore results in an increase in the total ON resistance (RON) of the MOSFET.
Prior art techniques to reduce the specific ON resistance of the Trench MOSFET rely on reduction of the cell pitch illustrated in FIG. 9. The increase of the breakdown voltage includes optimization of the trench depth and shape of the trench as shown in FIG. 10 (see Patent Reference 1, for example). FIG. 11 shows the MOSFET structure and doping profile to reduce the breakdown voltage degradation at the corner of the Trench (see Patent Reference 2, for example).
Besides the foregoing documents, the following documents describe other prior art techniques in relation to the Trench MOSFET: Patent Reference 3, which describes the semiconductor and the fabrication method thereof; Patent Reference 4 describing the p-channel Trench MOSFET, and Patent Reference 5 describing the semiconductor apparatus and the fabrication method thereof.    [Patent Reference 1] Specification of U.S. Pat. No. 5,168,331 (published on Dec. 1, 1992)    [Patent Reference 2] Specification of U.S. Pat. No. 4,893,160 (published on Jan. 9, 1990)    [Patent Reference 3] Japanese Unexamined Patent Publication No. 23092/1996 (Tokukaihei 8-23092) (published on Jan. 23, 1996)    [Patent Reference 4] Japanese Unexamined Patent Publication No. 354794/1999 (Tokukaihei 11-354794) (Dec. 24, 1999)    [Patent Reference 5] Japanese Unexamined Patent Publication No. 324197/2003 (Tokukai 2003-324197) (Nov. 14, 2003)    [Non-Patent Reference 1] Krishna Shenai, “Optimized Trench MOSFET Technologies for Power Devices”, IEEE Transactions on Electron Devices, vol. 39, no. 6, pp. 1435-1443, June 1992.